1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device having an electrically rewritable nonvolatile semiconductor memory device.
2. Description of the Related Art
A nonvolatile semiconductor memory device, particularly a NAND flash memory, is further miniaturized. Recently, a memory cell having an area of 2F×2F=4F2, where the minimum processing size is F, has been developed (Reference Document: Tsuneyuki Miyake, “Process leading to 16-Gbit NAND Flash, Realization of Ultimate Cell of 4F2 with 50 nm by TOSHIBA” NIKKEI Micro Devices, August, 2003, pp 57 to 62).
In a memory cell array in which the memory cells described above are integrated, the arrangement pitch of the element regions is 2F. Therefore, the arrangement pitch of bit lines becomes 2F and the arrangement pitch of bit line contacts which connect the bit lines to the diffusion layers of block selection transistors is also set to 2F.
However, unlike the element region pattern or bit line pattern, the bit line contact pattern is not a line pattern, but a hole pattern. The resolution of the hole pattern is lower than that of the line pattern and an error caused at the etching time is larger. Therefore, when memory cells having bit line contacts arranged at the pitch 2F are formed, the arrangement becomes extremely tight from a technical viewpoint.
Therefore, memory cells having bit line contacts arranged at twice the above pitch are described in Jpn. Pat. Appln. KOKAI Publication No. 2005-56989. In this specification, memory cells used in this type of memory cell array are called double-pitch cells.